Logic Gate Simulator — Build and Simulate Digital Logic Circuits
Logic gates are the fundamental building blocks of all digital electronics — every CPU, memory chip, and digital device is built from billions of these simple switching elements. The free logic gate simulator on PublicSoftTools lets you drag and drop gates to build circuits, set input values, and see outputs update in real time — making abstract digital logic concepts concrete and interactive.
Logic Gates Reference
| Gate | Symbol | Inputs | Output behaviour | CMOS implementation |
|---|---|---|---|---|
| AND | ∧ | 2+ | HIGH only when ALL inputs are HIGH | CMOS: NAND followed by NOT (inverter) |
| OR | ∨ | 2+ | HIGH when AT LEAST ONE input is HIGH | CMOS: NOR followed by NOT |
| NOT (Inverter) | ¬ | 1 | Output is OPPOSITE of input | Single PMOS + NMOS pair — simplest CMOS gate |
| NAND | ↑ | 2+ | LOW only when ALL inputs are HIGH (AND inverted) | Natural CMOS implementation; universal gate |
| NOR | ↓ | 2+ | HIGH only when ALL inputs are LOW (OR inverted) | Natural CMOS implementation; universal gate |
| XOR | ⊕ | 2 | HIGH when inputs DIFFER | Requires ~8 transistors; built from AND/OR/NOT |
| XNOR | ⊙ | 2 | HIGH when inputs are the SAME (XOR inverted) | XOR followed by inverter |
| Buffer | → | 1 | Output equals input (used for signal amplification/isolation) | Two inverters in series |
How to Use the Logic Gate Simulator
- Open the logic gate simulator.
- Drag gates from the toolbox onto the canvas — AND, OR, NOT, XOR, NAND, NOR, and more.
- Click the input terminals to add input pins (set to 0 or 1 by clicking).
- Click the output terminal to add output pins (shows computed value).
- Connect gates by clicking a gate's output pin and dragging to another gate's input pin. Wires automatically route.
- Toggle input values by clicking the input pins. Output values update instantly as you change inputs.
- Add clocks for sequential circuits — set frequency and use as a clock input for flip-flops.
Common Logic Circuits
| Circuit | Gates used | Function | Notes |
|---|---|---|---|
| Half adder | XOR + AND | Adds two 1-bit numbers; outputs sum and carry | Cannot accept carry-in from previous stage |
| Full adder | 2× XOR, 2× AND, 1× OR | Adds two 1-bit numbers plus carry-in; used in multi-bit adder chains | Single-bit operation; chain multiple for multi-bit addition |
| SR latch | 2× NOR (or 2× NAND) | Bistable memory: stores one bit; Set input → Q=1, Reset → Q=0 | Forbidden state when both S and R are active simultaneously |
| D flip-flop | SR latch + clock gating | Stores one bit synchronously with a clock signal | Most important storage element; basis of registers and memory |
| 2-to-1 multiplexer | 2× AND, 1× OR, 1× NOT | Selects one of two inputs to pass to output, controlled by a select line | Scales to 4-to-1, 8-to-1 etc. with additional gates |
| Decoder (2-to-4) | 4× AND, 2× NOT | Takes 2 input bits and activates exactly one of 4 output lines | Used in memory addressing to select a specific memory location |
From Gates to Transistors
Each logic gate is physically implemented using transistors — tiny semiconductor switches. Modern CMOS (Complementary Metal-Oxide-Semiconductor) technology uses pairs of PMOS and NMOS transistors. A NOT gate (inverter) uses one PMOS and one NMOS transistor; a NAND gate uses two PMOS in parallel and two NMOS in series, totalling four transistors.
The most complex processor chips contain over 100 billion transistors — all implementing logic gates arranged in massively complex combinational and sequential circuits. The simulator abstracts away transistor-level details to work at the gate level, which is where most digital logic design and education operates.
Combinational vs. Sequential Logic
Combinational logic
In combinational circuits, the output depends only on the current inputs — there is no memory of previous states. Logic gates connected without any feedback form combinational circuits. Examples: adders, decoders, multiplexers, encoders, comparators. The simulator lets you build and test combinational circuits by setting inputs and observing outputs.
Sequential logic
Sequential circuits have memory — outputs depend on both current inputs and past states. They contain feedback paths and typically include flip-flops or latches as memory elements. Sequential circuits are synchronised by a clock signal. Examples: registers, counters, shift registers, state machines, RAM. The simulator supports clock inputs and D flip-flops for building sequential circuits.
Building a Half Adder
A half adder adds two single bits A and B, producing a Sum and a Carry output:
- Sum = A XOR B (1 when exactly one input is 1; 0 when both are 0 or both are 1)
- Carry = A AND B (1 only when both inputs are 1 — carries to the next bit position)
To build this in the simulator: place one XOR gate and one AND gate. Connect both inputs A and B to both gates. The XOR gate output is Sum; the AND gate output is Carry. Test all four input combinations (00, 01, 10, 11) and verify: Sum truth table matches XOR, Carry matches AND.
NAND and NOR as Universal Gates
Any Boolean function — any logic circuit — can be built using only NAND gates, or alternatively using only NOR gates. This makes them "universal gates." Proving this involves showing that AND, OR, and NOT can all be constructed from NAND gates alone:
- NOT from NAND: Connect both inputs of a NAND gate together → output is NOT A (since NAND(A,A) = NOT(A AND A) = NOT A)
- AND from NAND: A NAND gate followed by a NOT-from-NAND inverter
- OR from NAND: Apply De Morgan's law: A OR B = NOT(NOT A AND NOT B). First invert both inputs (using NAND as inverter), then feed into a NAND gate.
In the simulator, challenge yourself to build an OR gate and an AND gate using only NAND gates. This exercise deepens understanding of Boolean algebra and why NAND is preferred in CMOS chip manufacturing.
Logic Minimisation
A logic function can often be implemented with fewer gates than the straightforward approach suggests. Minimisation techniques reduce gate count, which saves chip area, reduces power consumption, and can improve speed.
The main minimisation tools are:
- Boolean algebra: Apply laws (De Morgan's, distributive, etc.) algebraically to simplify the expression
- Karnaugh maps (K-maps): Visual method for minimising up to 6 variables by grouping adjacent 1s in a grid
- Quine-McCluskey algorithm: Systematic minimisation for larger variable counts; suitable for computer implementation
After minimising, the logic gate simulator can verify that the minimised circuit produces the same truth table as the original.
Propagation Delay and Timing
Real logic gates have a propagation delay — a small time between an input changing and the output responding. In complex circuits, signals travel through multiple gate levels, and delays accumulate. The critical path — the longest chain of gates between input and output — determines the maximum clock frequency a sequential circuit can run at.
The simulator works at the logical level without propagation delays (ideal gates). Real circuit simulators (SPICE, ModelSim, Verilog simulators) include timing models for accurate delay simulation.
Applications of Logic Gates
Arithmetic logic units (ALU)
The ALU is the computing core of every CPU. It implements arithmetic (addition, subtraction, multiplication) and logical (AND, OR, NOT, comparisons) operations using networks of full adders, multiplexers, and logic gates. Modern CPUs have multiple ALUs operating in parallel.
Memory cells
Static RAM (SRAM) stores bits using flip-flops (typically 6 transistors per cell). Dynamic RAM (DRAM) stores bits as charge on capacitors, requiring periodic refresh. Both rely on the bistable (two-stable-state) property of cross-coupled logic gates.
Cryptographic hardware
Encryption algorithms (AES, SHA-256) are implemented in hardware as combinational and sequential logic circuits. Dedicated hardware accelerators (HSMs, TPM chips, hardware wallets) implement cryptographic operations in custom logic for speed and security.
Common Questions
How many gates does it take to build a processor?
A simple 4-bit CPU can be built from a few hundred gates. The 8080 (Intel, 1974) had about 4,500 transistors (~2,250 gates). Modern CPUs use billions of transistors. The Apple M4 chip (2024) has ~28 billion transistors — the equivalent of hundreds of millions of two-input NAND gates.
What is the difference between a combinational circuit and a state machine?
A combinational circuit has no memory — its output depends only on current inputs. A state machine (sequential circuit) has memory — it can be in one of several defined states, and both the next state and the output depend on the current state and current inputs. Traffic lights, vending machines, and communication protocols are commonly modelled as state machines.
Do real logic gates work with exactly 0V and 5V?
Logic levels are defined as voltage ranges, not exact values. For a 5V CMOS circuit: 0–1.5V is LOW (logic 0); 3.5–5V is HIGH (logic 1); 1.5–3.5V is the undefined region (must not occur in normal operation). Modern CMOS runs at 1.8V, 1.2V, or even lower supply voltages for power efficiency. The simulator uses abstract 0/1 values rather than physical voltages.
Simulate Your Logic Circuit
Drag and drop gates, connect inputs, and see your circuit outputs update in real time — free, no signup.
Open Logic Gate Simulator